The present invention relates to a binary counter circuit, and more particularly to a counter circuit with low power consumption.
A counter is a register that goes through a predetermined sequence of states upon the application of input pulses, and is used for counting the numbers of occurrence of an event and are useful for generating timing signals to control the sequence of operations in digital computers. An n-bit binary counter is capable of sequentially incrementing or decrementing a binary value, and in detail goes through a sequence of binary numbers such as 0000, 0001, 0010, 0011, and so on. The n-bit binary counter which has n flip-flops synchronized with a clock signal and counts follows a sequence of states according to the binary count of n bits, from 0 to 2nxe2x88x921. Of the n-bit binary value, the lower-order bit is complemented after every count and every other bit is complemented from one count to the next if and only if all its lower-order bits are equal to 1. For example, the binary count from 0111(7) to 1000(8) is obtained by (a) complementing the lower-order bit, (b) complementing the second-order bit because the first bit of 0111 is 1, (c) complementing the third-order bit because the first two bits of 0111 are 1""s, and (d) complementing the fourth-order bit because the first three bits of 0111 are all 1""s.
As described immediately above, a higher-order bit, (nxe2x88x92m)-bit of the n-bit binary counter is complemented at the next operation after all bits of the lower m-bit are 1""s. In other hands, no the higher (nxe2x88x92m)-bit is complemented until all of the lower m-bit are 1""s.
The n-bit binary counter mentioned above as a prior art has a problem in that there is unnecessary power consumption in the binary counter because clocks are applied even to flip-flops corresponding to the higher (nxe2x88x92m)-bit where no data change is during the incrementing or decrementing operation thereof.
The present invention is intended to solve the problem, and it is an object of the invention to provide a low power consumption counter which has a clock gating circuit for preventing unnecessary power consumption.
It is the other object of the present invention to provide a lower power consumption counter wherein no flip-flops corresponding to the higher-order bit component are clock-toggled during the incrementing operation thereof until a carry signal is generated from the final one of flip-flops corresponding to the lower-order bit component.
According to one aspect of the present invention, an n-bit binary counter with low power consumption comprises a first adder section for adding a xe2x80x9c1xe2x80x9d to a lower-order m-bit component of an n-bit input signal and producing a carry signal when the lower-order m-bit component is all 1""s, said n-bit input signal having the lower-order m-bit component and a higher-order (nxe2x88x92m)-bit component; a second adder section for adding the carry signal to the higher-order (nxe2x88x92m)bit component; a first register for storing output of the first adder section in response to a first clock signal; a second register for storing output of the second adder section in response to a second clock signal; and means for receiving the first clock signal and the carry signal, and producing the second clock signal when the carry signal is generated from the first adder section. The n-bit input signal is composed of outputs of the first and second register sections.